View MAX3691_107809.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-1207; Rev 0; 3/97
KIT ATION EVALU E AILABL AV
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs
_______________General Description
The MAX3691 serializer is ideal for converting 4-bitwide, 155Mbps parallel data to 622Mbps serial data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers a 3.3V PECL serial-data output. A fully integrated PLL synthesizes an internal 622Mbps serial clock from a 155.52MHz reference clock. The MAX3691 is available in the extended-industrial temperature range (-40C to +85C), in a 32-pin TQFP package.
____________________________Features
o Single +3.3V Supply o 155Mbps Parallel to 622Mbps Serial Conversion o 215mW Power o LVDS Parallel Clock and Data Inputs o Differential 3.3V PECL Serial-Data Output
MAX3691
________________________Applications
622Mbps SDH/SONET Transmission Systems 622Mbps ATM/SONET Access Nodes Add/Drop Multiplexers Digital Cross Connects
______________Ordering Information
PART MAX3691ECJ TEMP. RANGE -40C to +85C PIN-PACKAGE 32 TQFP
Pin Configuration appears at end of data sheet.
___________________________________________________Typical Operating Circuit
0.1F LVDS CRYSTAL REFERENCE 0.1F
VCC = +3.3V PCLKI- PCLKI+ RCLK- RCLK+ PD0+ PD0OVERHEAD GENERATION PD1+ PD1PD2+ PD2PD3+ PD3PCLKO- PCLKO+ SD- SD+ VCC = +3.3V 130 130 1.5k 24.9k 100pF FILVCC = +3.3V VCC GND FIL+
MAX3691
MAX3667
82 82
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE (Z0 = 50)
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs MAX3691
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND) VCC .........................................................................-0.5V to 5V All Inputs.................................................-0.5V to (VCC + 0.5V) Output Current LVDS Outputs (PCLKO)................................................10mA PECL Outputs (SD).......................................................50mA Continuous Power Dissipation (TA = +85C) TQFP (derate 10.20mW/C above +85C) ...................663mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential LVDS loads = 100 1%, PECL loads = 50 1% to (VCC - 2V), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) PARAMETER Supply Current PECL OUTPUTS (SD) Output High Voltage Output Low Voltage VOH VOL TA = +25C to +85C TA = -40C TA = +25C to +85C TA = -40C Differential input voltage = 100mV Common-mode voltage = 50mV VCC - 1.03 VCC - 1.08 VCC - 1.81 VCC - 1.95 VCC - 0.88 VCC - 0.88 VCC - 1.62 VCC - 1.62 V V SYMBOL ICC CONDITIONS PECL outputs unterminated MIN 38 TYP 65 MAX 100 UNITS mA
LVDS INPUTS AND OUTPUTS (PCLKI, RCLK, PCLKO, PD_) Input Voltage Range Differential Input Threshold Threshold Hysteresis Differential Input Resistance Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Single-Ended Output Resistance Change in Magnitude of Single-Ended Output Resistance for Complementary States VI VIDTH VHYST RIN VOH VOL VOD VOD VOS VOS RO RO 40 70 1 TA = +25C 1.125 0.925 250 400 25 1.275 25 140 10 85 0 -100 70 100 115 1.475 2.4 100 V mV mV V V mV mV V mV %
2
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential LVDS load = 100 1%, PECL loads = 50 1% to (VCC - 2V) TA = +25C, unless otherwise noted. Typical values are at VCC = +3.3V.) (Note 1) PARAMETER Serial Clock Rate Parallel Data-Setup Time Parallel Data-Hold Time PCLKO to PCLKI Skew Output Jitter PECL Differential Output Rise/Fall Time SYMBOL fSCLK tSU tH tSKEW 0 tR, tF TA = -40C to +85C (Note 2) 400 200 600 -0.7 +3.3 13 CONDITIONS MIN TYP 622.08 MAX UNITS MHz ps ps ns psRMS ps
MAX3691
Note 1: AC characteristics guaranteed by design and characterization. Note 2: Assumes a 50% duty cycle 5%.
__________________________________________Typical Operating Characteristics
(VCC = +3.0V to +3.6V, differential LVDS loads = 100, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3691-01
PARALLEL DATA-SETUP TIME vs. TEMPERATURE
MAX3691-02
PARALLEL DATA-HOLD TIME vs. TEMPERATURE
MAX3691-03
100
-20 PARALLEL DATA-SETUP TIME (ps)
250 PARALLEL DATA-HOLD TIME (ps)
80 SUPPLY CURRENT (mA)
-40
230
60
-60
210
40
-80
190
20
-100
170
0 -50 -25 0 25 50 75 100 TEMPERATURE (C)
-120 -50 -25 0 25 50 75 100 TEMPERATURE (C)
150 -50 -25 0 25 50 75 100 TEMPERATURE (C)
_______________________________________________________________________________________
3
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs MAX3691
____________________________Typical Operating Characteristics (continued)
(VCC = +3.0V to +3.6V, differential LVDS loads = 100, unless otherwise noted.)
PCLKO-to-PCLKI SKEW vs. TEMPERATURE
MAX3691-04
SERIAL-DATA OUTPUT EYE DIAGRAM (622Mbps, 27-1 PRBS)
MAX3691-05
SERIAL-DATA OUTPUT JITTER
MAX3691-06
6
1.21V
908mV
PCLKO-TO-PCLKI SKEW (ns)
4
OC-12 SONET MASK
2 62mV/ div
10mV/ div fRCLK = 155.52MHz
0
-2 0.59V -50 -25 0 25 50 75 100 161ps/div Mean 23.88ns RMS 8.418ps PkPk 70.2ps TEMPERATURE (C) 808mV 10ps/div 1 68.774% 2 95.534% 3 99.738%
-4
______________________________________________________________Pin Description
PIN 1, 3, 5, 7 2, 4, 6, 8 9, 17, 18, 19, 24, 25, 32 10 11 12, 13, 16, 20, 21, 28, 29 14 15 22 23 26 27 30 31 4 NAME PD0+ to PD3+ PD0- to PD3GND PCLKOPCLKO+ VCC SDSD+ FILFIL+ RCLK+ RCLKPCLKI+ PCLKIFUNCTION Noninverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal's positive transition. Inverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal's positive transition. Ground Inverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit. Noninverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit. +3.3V Supply Voltage Inverting PECL Serial-Data Output Noninverting PECL Serial-Data Output Filter Capacitor Input. See Typical Operating Circuit for external-component connections. Filter Capacitor Input. See Typical Operating Circuit for external-component connections. Noninverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock (155.52MHz) to the RCLK inputs. Inverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock (155.52MHz) to the RCLK inputs. Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. Inverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs
_______________Detailed Description
The MAX3691 serializer comprises a 4-bit parallel input register, a 4-bit shift register, control and timing logic, a PECL output buffer, LVDS input/output buffers, and a frequency-synthesizing PLL (consisting of a phase/ frequency detector, loop filter/amplifier, and voltagecontrolled oscillator). This device converts 4-bit-wide, 155Mbps data to 622Mbps serial data (Figure 1). The PLL synthesizes an internal 622Mbps reference used to clock the output shift register. This clock is generated by locking onto the external 155.52MHz reference-clock signal (RCLK).
MAX3691
The incoming parallel data is clocked into the MAX3691 on the rising transition of the parallel-clockinput signal (PCLKI). The control and timing logic ensure proper operation if the parallel-input register is latched within a window of time that is defined with respect to the parallel-clock-output signal (PCLKO). PCLKO is the synthesized 622Mbps internal serialclock signal divided by four. The allowable PCLKO-toPCLKI skew is -0.7ns to +3.3ns. This defines a timing window at about the PCLKO rising edge, during which a PCLKI rising edge may occur. Figure 2 is the timing diagram.
PD3+ PD3LVDS
MAX3691
4-BIT PARALLEL INPUT REGISTER
PD2+ PD2LVDS
PD1+ PD1LVDS
PD0+ PD0LVDS
PCLKI+ LVDS PCLKISHIFT 4-BIT SHIFT REGISTER PECL SD+ SD-
RCLK+ LVDS RCLK-
PHASE/FREQ DETECT
VCO
CONTROL
LATCH
LVDS
FIL+ FIL-
PCLKO+ PCLKO-
Figure 1. Functional Diagram
_______________________________________________________________________________________
5
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs MAX3691
PCLKO
tSKEW
PCLKI tSU PD_ VALID PARALLEL DATA* tH
SD
D3
D2
D1
D0
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-). *PD3 = D3; PD2 = D2; PD1 = D1; PD0 = D0.
Figure 2. Timing Diagram
Low-Voltage Differential-Signal (LVDS) Inputs and Outputs
The MAX3691 features LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 250mV-400mV differential low-voltage swings to achieve fast transition times, minimized power dissipation, and noise immunity. For proper operation, the parallel-clock LVDS outputs (PCLKO+, PCLKO-) require 100 differential DC termi-
nation between the inverting and noninverting outputs. Do not terminate these outputs to ground. The parallel data and parallel clock LVDS inputs (PD_+, PD_-, PCLKI+, PCLKI-) are internally terminated with 100 differential input resistance, and therefore do not require external termination.
PECL Outputs
The serial-data PECL outputs (SD+, SD-) require 50 DC termination to (VCC - 2V). See the Alternative PECLOutput Termination section.
6
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs
__________Applications Information
Alternative PECL-Output Termination
Figure 3 shows alternative PECL output-termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If AC coupling is necessary, be sure that the coupling capacitor is placed following the 50 or Thevenin-equivalent DC termination.
TOP VIEW
GND FIL+ FILVCC VCC GND GND GND
__________________Pin Configuration
MAX3691
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled-impedance transmission lines to interface with the MAX3691 clock and data inputs and outputs.
GND RCLK+ RCLKVCC VCC PCLKI+ PCLKIGND
25 26 27 28 29 30 31 32
MAX3691
VCC SD+ SDVCC VCC PCLKO+ PCLKOGND
+3.3V 130
130
MAX3691
SD+ Z0 = 50 PECL INPUTS
___________________Chip Information
TRANSISTOR COUNT: 1633
SD-
Z0 = 50 82 82
MAX3691
SD+ Z0 = 50 HIGHIMPEDENCE INPUTS
SD-
Z0 = 50
50 VCC - 2V
50
Figure 3. Alternative PECL-Output Termination
_______________________________________________________________________________________
PD0+ PD0PD1+ PD1PD2+ PD2PD3+ PD3-
1 2 3 4 5 6 7 8
TQFP
7
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs MAX3691
________________________________________________________Package Information
TQFPPO.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX3691

	To Download MAX3691 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .